1. Field of the Invention
The present invention relates to the field of digital systems, in particular, digital systems having embedded random access memory (RAM) including general and special purpose computer systems. More specifically, the present invention relates to the addressing apparatus provided on these digital systems for providing access addresses to the embedded RAM.
2. Background
Reduction of power consumption has become increasingly important for the design of compact digital systems having a very large number of integrated electronics, such as microprocessor-based and battery-powered computer systems. Reduction of power consumption not only conserve the power available thereby extending the operating life of battery-powered digital systems between recharges, it also reduces the number of power and ground pins required thereby reducing device package pin requirements.
In the case of microprocessor-based and battery-powered computer systems, a number of approaches to reduce power consumption has been developed in the industry. For example, the Intel.RTM. 80.times.86 microprocessors provide a transparent system management interrupt and an elaborate list of affiliated hardware/software controls for selectively shutting down idle peripheral devices and suspending system operation to reduce power consumption and conserve power. For further description of system and power management under the Intel.RTM. 80.times.86 microprocessors, see various product literature provided by Intel Corporation of Santa Clara, Calif.
However, the problem of reducing power consumption or minimizing device package pins is never totally solved. Additional reduction is always desirable as long as it is cost effective, not just economically, but also from the perspective of hardware real estate cost. Since digital systems having embedded RAM typically have multiple banks of RAM, and the RAM are constantly addressed through one or more address buses, even a small amount of reduction in power consumption for each addressing of the RAM can result in a significant amount of reduction in power consumption by the address buses. In turn, a significant amount of power would be conserved, and a significant number of device package pins will be eliminated.
Typically, one or more banks of the RAM are dedicated to functions that will access them only in a sequential manner. A particular example of such dedicated RAM is RAM used exclusively for tracing on a digital data instrumentation system. Even for the RAM that are not exclusively accessed in a sequential manner, inevitably at one time or another, a series of accesses to an area of the RAM will be made sequentially. Both of these situations, due to the inherent characteristics of sequential accesses, provide yet another opportunity for reducing power consumption by the digital system. As will be disclosed, the RAM addressing apparatus of the present invention reduces its power consumption by exploiting the inherent characteristics of sequential accesses, thereby achieving the above described desirable results of further enhancement in power conservation and device package pin reduction. As will be obvious from the description to follow, the RAM addressing apparatus of the present invention has particular application to microprocessor-based and battery-powered computer systems.